Integrated semiconductor memory circuits, particularly those employing cells which include essentially only a storage capacitor and a switch, have achieved high densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard, wherein the switch is a single field effect transistor.
In commonly assigned U.S. Pat. No. 3,979,734, filed June 16, 1975, by W. David Pricer and J. E. Selleck, there is described a memory array made of small cells each of which employs a storage capacitor and a single bipolar transistor. In this memory array, which is word organized, each storage capacitor of these cells has one capacitor terminal connected to a separate bit/sense line to provide a fast, dense bipolar memory.
In another commonly assigned U.S. Pat. No. 4,040,017, filed Mar. 31, 1976, by H. S. Lee, there is disclosed a capacitor memory produced in a unipolar technology which is provided with very small cells, each of which includes substantially only a storage capacitor having a bit/sense line connected to one terminal of the capacitor and a word line providing a coupling to the other terminal of the capacitor.
In still another commonly assigned U.S. Pat. No. 3,819,959, filed Dec. 4, 1970, by J. J. Chang and J. W. Sumilas, there is disclosed a very dense memory having cells connected serially as in a shaft register. This memory which has very small cells is operated so as to continuously transfer packets of charge representative of data from one cell to an adjacent cell until the charge reaches an output terminal. This type of memory is commonly called a charge coupled or charge transfer device memory.
Since only a very small charge is contained in each cell of these dense memories, sensing systems used to detect the charge must of necessity be very sensitive charge or voltage detectors to distinguish between different binary bits of data stored in the cells.
An amplifier which has been found to be very suitable for detecting small signals, particularly in the cells which employ a storage capacitor and a field effect transistor, as disclosed in the above identified U.S. Pat. No. 3,387,286, is described in commonly assigned U.S. Pat. No. 3,993,917, filed May 29, 1975, by H. L. Kalter. This amplifier includes a pair of cross-coupled field effect transistor devices coupled to a pair of bit/sense lines by clock signal responsive switching devices and is process parameter independent.
Another detecting system which has been found to be very suitable for detecting very small charges or voltages in memory cells is described in commonly assigned U.S. Pat. No. 3,764,906, filed Oct. 1, 1971, by L. G. Heller. In this detecting system the amount of charge stored in a charge storage medium is transferred with negligible loss from the storage medium to a charge detector without regard to the size of any distributed or parasitic capacitance present on the lines, such as on a bit line.
In order to provide memory systems which have even more dense storage of information than in the memories disclosed hereinabove. Memories have been provided wherein the storage capacity is increased by utilizing multiple levels of charge in a given cell to simultaneously represent two or more digits of information. In these multilevel charge storage memories, the storage medium may store N bits of information, where N is equal to 2, 3 or more and where the number of levels is equal to 2.sup.N. A charge coupled device memory of this type is disclosed in commonly assigned U.S. Pat. No. 4,139,910, filed Dec. 6, 1976, by N. G. Anantha, F. Y. Chang and B. J. Rubin.
In an article entitled "Multilevel Random-Access Memory Using One Transistor Per Cell" by R. A. Heald, et. al., in IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 519 through 528, there is described a multilevel random access memory which uses junction field effect transistors, with current sensing for the detection of the information stored in these cells.
In the prior art many circuits are known for handling with precision small quantities of charge. For example, in commonly assigned U.S. Pat. No. 4,035,667, filed Dec. 2, 1975, by L. G. Heller, there is described an integrated circuit for inserting charge packets into a charge transfer device, in commonly assigned U.S. Pat. No. 4,137,464, filed Aug. 16, 1977, by L. G. Heller and L. M. Terman there is disclosed a technique for producing charge packets having values Q/2, Q/4, Q/8 . . . Q/2.sup.N where Q is the original size of the charge packet and N is an integer, and in an article entitled "Convertor for CCD Multilevel Shift Registers" by H. S. Lee, in IBM Technical Disclosure Bulletin Vol. 20, No. 8 January 1978, pp. 3011-3013, there is described another system for producing fractional charge packets which may be used in memory systems.